1. Field of the Invention
The present invention generally relates to an electro-static discharge (ESD) protection circuit (ESD). More particularly, the present invention relates to an electro-static discharge (ESD) protection circuit for a dual polarity input/output (I/O) pad.
2. Description of the Related Art
The electro-static discharge (ESD) is a phenomenon of the motion of the static electricity generated from a non-conductive surface, and the electro-static discharge (ESD) may damage the component circuits and the semiconductors in the integrated circuit (IC). For example, a human body moving on a carpet may gather several hundred to thousand voltages of static electricity in an environment having a higher relative humidity, and may gather more than ten thousand voltages of static electricity in an environment having a lower relative humidity. In an apparatus for packaging the integrated circuits (ICs) or an apparatus for testing the integrated circuits (ICs), several hundred to thousand voltages of static electricity may also be generated. When a chip is contacted by the electro-static charged body including, for example, the human body, the apparatus or the device described above, the chip will be discharged and the phenomenon is the so-called electro-static discharge (ESD). The surge power of the electro-static discharge (ESD) may damage the integrated circuits (ICs) in the chip.
In order to prevent the damage of the integrated circuits (ICs) due to the electro-static discharge (ESD) phenomenon, in general an electro-static discharge (ESD) protection circuit will be formed in the integrated circuit (IC). Conventionally, the electro-static discharge (ESD) protection circuit is composed of the NMOS transistor or the CMOS transistor, and is provided by the parasitic bipolar junction transistor (parasitic BJT) or the silicon control rectifier (SCR) formed by these transistors to achieve the electro-static discharge (ESD) protection effect. However, the electro-static discharge (ESD) protection circuit is effective if and only if the electro-static discharge (ESD) protection effect is provided without influencing the normal operation of the device.
With respect to the electro-static discharge (ESD) protection circuit, a proper design for the activating voltage is necessary. In other words, when the device is in normal operation, the electro-static discharge (ESD) protection circuit should not be activated unexpectedly. For a device having a dual polarity input/output (I/O) pad, the detection of the static electricity can be classified into a positive polarity situation and a negative polarity situation. In general, when the electro-static discharge (ESD) protection circuit is being attacked by an electro-static current, the circuit may not be burnt or shorted by the heat generation. This is because the current-voltage characteristic (I-V curve) of the parasitic diode or bipolar junction transistor formed by the electro-static discharge (ESD) protection circuit have a characteristics at a high current as shown in FIG. 1. Thus, the circuit design of the electro-static discharge (ESD) protection circuit described above can be practically applied.
However, when the ESD device is operated under a negative bias, because the pn junction existed by nature is capable of only forming a forward-bias diode. The current-voltage characteristic (I-V curve) of the forward-bias diode is shown as the curve in the fourth quadrant of FIG. 1. In the meanwhile, when the device is in normal operation and under a negative bias, the electro-static discharge (ESD) protection circuit may be activated. In other words, when the device is in normal operation and under a negative bias, the electro-static discharge (ESD) protection circuit will adversely influence the normal operation of the device.